A Hierarchical Hybrid Optical-Electronic Clos Architecture for Network-on-Chip

With more and more processor cores integrated on a chip, Networks-on-chip (NoC) is emerging as a candidate architecture for multiprocessor systems-on-chip (MPSoC). Traditional metallic interconnects have become the bottleneck of NoC due to the limited bandwidth, long delay, and high power consumption. Optical Network-on-Chip (ONoC) can decrease interconnect delay and provide higher bandwidth with lower power consumption. In this paper, we propose a Clos-based Hierarchical Optical-Electronic NoC, called CHONoC, which can take advantage of both optical routers and interconnects in a hierarchical manner. CHONoC employs novel desgins including two different topologies in optical layer and electric layers, communication mechanism with high path diversity, and two optical symmetric routers with strictly non-blocking property. Simulation results show that CHONoC can achieve small latency and high throughput especially for high local traffics compared with Mesh-based, Cmesh-based and Clos(8,8,8)-based ONoCs. Keywords-Optical Network-on-Chip; Clos network; Optical router; topology; floorplan. 1. INRTODUCTION With the rapid development of the integrated technology, the 90nm and 65nm technology has entered the mass production stage and the processor produced by 45nm technology has been already on the market. The International Technology Roadmap for Semiconductors (ITRS) projects that the IC manufacturing technology will reach 18nm by 2018[1]. With the feature size of the chips into the nanometer era, some problems such as high clock frequency, narrow metal line's width, and interconnect delay inside the chip, have become the main factors affecting the signal delay. Among these factors, the interconnect delay has become a big challenge in today's VLSI system design, and how to reduce the interconnect delay becomes the key factor to improve the performance of the system. Moreover, ITRS predicts that the local clock frequency will grow to 73GHz by 2020 and the on-chip communications need to meet the new demand for high-bandwidth applications. The problems of limited bandwidth, high latency, increasing power consumption and other problems associated with traditional metal interconnects will be the bottlenecks of the NoC performance improvement. Therefore, at the given power budget, the electric NoC may not be able to meet the demand of future application in terms of bandwidth and delay[2][3]. The optical interconnects as an effective way to solve the potential problems of electrical interconnect has been the highlight in the recent years. With the advances in semiconductor and circuit integrated technologies, a variety of integrated optical devices compatible with the CMOS have been made providing good opportunities for the optical interconnect technology applications on the network. Compared with the conventional metal interconnect, the optical interconnects has many advantages: larger bandwidth, lower power consumption, and smaller signal delay etc. Recent advances in nanoscale silicon photonics and optical devices have led to the development of Optical [Research Notes by Yawen Chen]: This is a draft version of a collaboration work with Huaxi Gu’s Research Group from Xidian Universtity. The design in this work used a combination of an on-chip electronic (for local traffic) and an on-chip optical network (for inter-cluster traffic) by taking advantages of both NoC and ONoCs. In our future work, we will investigate the tradeoffs among the performance, reliablity and complexity of ONoCs from the networking perspective.